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cy7c6431x cy7c6434x cy7c6435x encore? v full speed usb controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-12394 rev. *r revised november 20, 2013 encore? v full speed usb controller features powerful harvard-architecture processor ? m8c processor speeds running up to 24 mhz ? low power at high processing speeds ? interrupt controller ? 3.0 v to 5.5 v operating voltage without usb ? operating voltage with usb enabled: ? 3.15 v to 3.45 v when supply voltage is around 3.3 v ? 4.35 v to 5.25 v when supply voltage is around 5.0 v ? commercial temperature range: 0c to +70c ? industrial temperature range: ?40 c to +85 c flexible on-chip memory ? up to 32 kb flash program storage: ? 50,000 erase and write cycles ? flexible protection modes ? up to 2048 bytes sram data storage ? in-system serial programming (issp) complete development tools ? free development tool psoc designer? ? full-featured, in-circuit emulator and programmer ? full-speed emulation ? complex breakpoint structure ? 128-kb trace memory precision, programmable clocking ? crystal-less oscillator with support for an external crystal or resonator ? internal 5.0% 6, 12, or 24 mhz main oscillator (imo): ? 0.25% accuracy with oscill ator lock to usb data, no external components required ? internal low-speed oscillator (ilo) at 32 khz for watchdog and sleep. the frequency range is 19 to 50 khz with a 32-khz typical value programmable pin configurations ? up to 36 general purpose i/o (gpio) depending on package. ? 25 ma sink current on all gpio ? 60ma total sink current on even port pins and 60 ma total sink current on odd port pins ? 120 ma total sink current on all gpios ? pull-up, high z, open drain, cmos drive modes on all gpio ? cmos drive mode a -5 ma source current on ports 0 and 1 and 1 ma on ports 2, 3, and 4 ? 20 ma total source current on all gpios ? low dropout voltage regulator for port 1 pins: ? programmable to output 3.0, 2.5, or 1.8 v ? selectable, regulated digital i/o on port 1 ? configurable input threshold for port 1 ? hot-swappable capability on port 1 full-speed usb (12 mbps) ? eight unidirectional endpoints ? one bidirectional control endpoint ? usb 2.0-compliant: tid# 40000893 ? dedicated 512 bytes buffer ? no external crystal required additional system resources ? configurable communication speeds ? i 2 c slave: ? selectable to 50 khz, 100 khz, or 400 khz ? implementation requires no clock stretching ? implementation during sleep modes with less than 100 ? a ? hardware address detection ? spi master and spi slave: ? configurable between 46.9 khz and 12 mhz ? three 16-bit timers ? 10-bit adc used to monitor ba ttery voltage or other signals with external components ? watchdog and sleep timers ? integrated supervisory circuit system bus 6/12/24 mhz internal main oscillator cpu core (m8c) srom 8k/16k/32k flash system resources i2c slave/spi master-slave por and lvd system resets port 1 port 0 sleep and watchdog full speed usb port 3 port 2 prog. ldo sram 2048 bytes interrupt controller encore v core 3 16-bit timers port 4 adc encore v block diagram errata: for information on silicon errata, see ?errata? on page 35. details include trigger conditions, devices affected, and proposed workaround.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 2 of 40 contents functional overview ........................................................ 3 the encore v core .................................................... 3 full-speed usb ........................................................... 3 10-bit adc ................................................................... 4 spi ............................................................................... 4 i2c slave ..................................................................... 5 additional system resources ..................................... 6 getting started .................................................................. 6 application notes ........................................................ 6 development kits ........................................................ 6 training ....................................................................... 6 cypros consultants .................................................... 6 solutions library .......................................................... 6 technical support ....................................................... 6 development tools .......................................................... 7 psoc designer software subsyst ems .......... .............. 7 designing with psoc designer ....................................... 8 select user modules ................................................... 8 configure user modules .............................................. 8 organize and connect .............. .............. ........... ......... 8 generate, verify, and debug ....................................... 8 pin configuration ............................................................. 9 16-pin part pinout ........................................................ 9 32-pin part pinout ...................................................... 10 48-pin part pinout ...................................................... 11 register reference ......................................................... 13 register conventions .................................................... 13 register mapping tables ............................................... 13 electrical specifications ................................................ 16 absolute maximum ratings ... .................................... 17 operating temperature ............................................. 17 dc electrical characteristics ..................................... 18 ac electrical characteristics ..................................... 22 package diagram ............................................................ 29 packaging dimensions .............................................. 29 package handling ..................................................... 31 thermal impedances ................................................. 31 capacitance on crystal pins .. ............. .............. ........ 31 solder reflow peak temperat ure ............................. 31 ordering information ...................................................... 32 ordering code definitions ..... .................................... 33 acronyms ........................................................................ 34 document conventions ................................................. 34 units of measure ....................................................... 34 numeric naming .................... .................................... 34 errata ............................................................................... 35 cy7c643xx errata summary .. .................................. 35 document history page ................................................. 37 sales, solutions, and legal information ...................... 40 worldwide sales and design s upport ......... .............. 40 products .................................................................... 40 psoc? solutions ...................................................... 40 cypress developer community ................................. 40 technical support ................. .................................... 40
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 3 of 40 functional overview the encore v family of devices are designed to replace multiple traditional full-speed usb microcontroller system components with one, low cost single-chip programmable component. communication peripherals (i 2 c/spi), a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the architecture for this device family, as illustrated in the encore v block diagram on page 1 , consists of two main areas: the cpu core and the system re sources. depending on the encore v package, up to 36 gpio are also included. this product is an enhanced version of cypress?s successful full speed-usb peripheral controllers. enhancements include faster cpu at lower voltage operation, lower current consumption, twice the ram and flash, hot-swappable i/os, i 2 c hardware address recognition, new very low current sleep mode, and new package options. the encore v core the encore v core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo and ilo. the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four-mips, 8-bit harvard architecture microprocessor. during usb operation, the cpu speed can be set to any setting. be aware that usb throughput decreases with a decrease in cpu speed. for maximum throughput, the cpu clock should be made equal to the system clock. the system clock must be 24 mhz for usb operation. system resources provide additional capability, such as a configurable i 2 c slave and spi master-slave communication interface and various system re sets supported by the m8c. full-speed usb the encore v usb system resource adheres to the usb 2.0 specification for full speed devices operating at 12 mb/second with one upstream port and one usb address. encore v usb consists of these components: serial interface engine (sie) block. psoc memory arbiter (pma) block. 512 bytes of dedicated sram. a full-speed usb transceiver with internal regulator and two dedicated usb pins. figure 1. usb transceiver regulator at the encore v system level, the full-speed usb system resource interfaces to the rest of the encore v by way of the m8c?s register access instructions and to the outside world by way of the two usb pins. the sie supports nine endpoints including a bidirectional control endpoint (endpoint 0) and eight unidirectional data endpoints (endpoints 1 to 8). the unidirectional data endpoints are individually configurable as either in or out. low value series resistors r ext (22 ? ) must be added externally to the d+ and d? lines to meet the driving impedance requirement for full-speed usb. the usb serial interface engine (sie) allows the encore v device to communicate with the usb host at full speed data rates (12 mb/s). the sie simplifies the interface to usb traffic by automatically handling the following usb processing tasks without firmware intervention: translates the encoded received data and formats the data to be transmitted on the bus. generates and checks cyclical redundancy checks (crcs). incoming packets failing che cksum verification are ignored. checks addresses. ignores all transactions not addressed to the device. sends appropriate ack/ nak/stall handshakes. identifies token type (setup, in, out) and sets the appropriate token bit once a valid token in received. identifies start-of-frame (sof) and saves the frame count. sends data to or retrieves data from the usb sram, by way of the psoc memory arbiter (pma). voltage regulator 5v 3.3v 1.5k 5k ps2 pull up dp dm ten td pdn rd dpo rse0 dmo receivers transmitter
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 4 of 40 firmware is required to handle various parts of the usb interface. the sie issues interrupts after key usb events to direct firmware to appropriate tasks: fill and empty the usb data buffers in usb sram. enable pma channels appropriately. coordinate enumeration by decoding usb device requests. suspend and resume coordination. verify and select data toggle values. 10-bit adc the adc on encore v device is an independent block with a state machine interface to cont rol accesses to the block. the adc is housed together with the temperature sensor core and can be connected to this or the analog mux bus. as a default operation, the adc is connec ted to the tem perature sensor diodes to give digital values of the temperature. figure 2. adc system performance block diagram the adc user module contains an integrator block and one comparator with positive and ne gative input set by the muxes. the input to the integrator stage comes from the analog global input mux or the temperature se nsor with an input voltage range of 0 v to v refadc . in the adc only configuration (the adc mux selects the analog mux bus, not the default tem perature sensor connection), an external voltage can be connected to the input of the modulator for voltage conversion. the ad c is run for a number of cycles set by the timer, depending upon the desired resolution of the adc. a counter counts the number of trips by the comparator, which is proportional to the input voltage. the temp sensor block clock speed is 36 mhz and is divided down to 1 to 12 mhz for adc operation. spi the serial peripheral interconn ect (spi) 3-wire protocol uses both edges of the clock to enable synchronous communication without the need for stringent setup and hold requirements. figure 3. basic spi configuration a device can be a master or sl ave. a master outputs clock and data to the slave device and inputs slave data. a slave device inputs clock and data from the master device and outputs data for input to the master. together, the master and slave are essentially a circular shift register, where the master generates the clocking and initiates data transfers. a basic data transfer occurs when the master sends eight bits of data, along with eight clocks. in any transfer, both master and slave transmit and receive simultaneously. if the master only sends data, the received data from the slave is ignored. if the master wishes to receive data from the slave, the master must send dummy bytes to generate the clocking for the slave to send data back. figure 4. spi block diagram interface block command/ status adc temp diodes v in system bus temp sensor/ adc interface to the m8 c ( processor ) core spi master spi slave mosi miso sclk data is output by both the master and slave on one edge of the clock. data is registered at the input of both devices on the opposite edge of the clock. spi block registers sysclk data_out data_in clk_in clk_out int ss_ sclk mosi, miso sclk mosi, miso configuration[7:0] control[7:0] transmit[7:0] receive[7:0]
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 5 of 40 spi configuration register (spi_cfg) sets master/slave functionality, clock speed, and interrupt select. spi control register (spi_cr) provides four control bits and four status bits for device interfacing and synchronization. the spim hardware has no support for driving the slave select (ss_) signal. the behavior and use of this signal is dependent on the application and encore v device and, if required, must be implemented in firmware. there is an additional data input in the spis, slave select (ss_), which is an active low signal. ss_ must be asserted to enable the spis to receive and transmit. ss_ has two high level functions: to allow for the selection of a given slave in a multi-slave environment. to provide additional clocking for tx data queuing in spi modes 0 and 1. i 2 c slave the i 2 c slave enhanced communications block is a serial-to-parallel processor, designed to interface the encore v device to a two-wire i 2 c serial communications bus. to eliminate the need for excessive cpu intervention and overhead, the block provides i 2 c-specific support for stat us detection and generation of framing bits. by default, the i 2 c slave enhanced module is firmware compatible with the previous generation of i 2 c slave functionality. however, this module provides new features that are configurable to implement significant flexibility for both internal and external interfacing. the basic i 2 c features include: slave, transmitter, and receiver operation. byte processing for low cpu overhead. interrupt or polling cpu interface. support for clock rates of up to 400 khz. 7- or 10-bit addressing (through firmware support). smbus operation (through firmware support). enhanced features of the i 2 c slave enhanced module include: support for 7-bit hardware address compare. flexible data buffering schemes. a ?no bus stalling? operating mode. a low power bus monitoring mode. the i 2 c block controls the data (sda) and the clock (scl) to the external i 2 c interface through direct connections to two dedicated gpio pins. when i 2 c is enabled, these gpio pins are not available for general purpose use. the encore v cpu firmware interacts with the block through i/o register reads and writes, and firmware synchronization is implemented through polling and/or interrupts. in the default operating mode, which is firmware compatible with previous versions of i 2 c slave modules, the i 2 c bus is stalled upon every received address or byte, and the cpu is required to read the data or supply data as required before the i 2 c bus continues. however, this i 2 c slave enhanced module provides new data buffering capability as an enhanced feature. in the ezi 2 c buffering mode, the i 2 c slave interface appears as a 32-byte ram buffer to the external i 2 c master. using a simple predefined protocol, t he master controls the read and write pointers into the ram. when this method is enabled, the slave never stalls the bus. in this pr otocol, the data available in the ram (this is managed by the cpu) is valid. figure 5. i 2 c block diagram i2c core i2c basic configuration i2c_cfg i2c_scr i2c_dr plus features hw addr cmp buffer module cpu port buffer ctl 32 byte ram i2c plus slave i2c_addr sda_out scl_in sysclk i2c_en to/from gpio pins standby scl_out sda_in i2c_xstat i2c_xcfg i2c_buf i2c_bp i2c_cp mcu_cp mcu_bp system bus
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 6 of 40 additional system resources system resources, some of which have been previously listed, provide additional ca pability useful to complete systems. additional resources include low voltage detection and power on reset. the following statements describe the merits of each system resource. low voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced por (power on reset) circuit el iminates the need for a system supervisor. the 5 v maximum input, 1.8, 2.5, or 3 v selectable output, ldo regulator provides regulation for i/os. a register controlled bypass mode enables the user to disable the ldo. standard cypress psoc ide tools are available for debugging the encore v family of parts. getting started the quickest path to understanding the encore v silicon is by reading this data sheet and usi ng the psoc designer integrated development environment (ide). this datasheet is an overview of the psoc integrated circuit and pr esents specific pin, register, and electrical specifications. fo r in-depth information, along with detailed programming information, see the encore? v cy7c643xx, encore? v lv cy7c604xx technical reference manual (trm) for this psoc device. for up-to-date ordering, packaging , and electrical specification information, see the latest psoc device data sheets on the web at http://www.cypress.com . application notes application notes are an excellent introduction to the wide variety of possible psoc designs and are available at http://www.cypress.com . development kits psoc development kits are available online from cypress at http://www.cypress.com and through a growing number of regional and global distributors, including arrow, avnet, digi-key, farnell, future elec tronics, and newark. training free psoc technical traini ng (on demand, webinars, and workshops) is available online at http://www.cypress.com . the training covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant, go to http://www.cypress.com and look for cypros consultants. solutions library visit our growing library of solution-focused designs at http://www.cypress.com . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support for assistance with technical issues, search knowledgebase articles and forums at http://www.cypress.com . if you cannot find an answer to your question, call technical support at 1-800-541-4736.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 7 of 40 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application requirements. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical us er interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/transmitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (dacs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc?s resources for a given application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs fo r the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu regist ers, set and clear breakpoints, and provide program run, halt , and step control. the debugger also allows you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. th is system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a ba se unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24-mhz) operation.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 8 of 40 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of use r-selectable functions. the psoc development process is: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called user modules. user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each eight bits of resolution. using these parameters, you can establish the pulse width and duty cycle. configure the parameters and properties to correspond to your chosen application. enter va lues directly or by selecting values from drop-down menus. all of the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module data sheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. organize and connect build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabilities rival those of syst ems costing many times more. in addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. it allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 9 of 40 pin configuration the encore v usb device is available in a variety of packages which are listed and illustrated in the subsequent tables. 16-pin part pinout figure 6. cy7c64315/cy7c64316 16-pin encore v usb device d+ qfn (top view) p2[3] p1[5] p1[1] v ss 16 15 14 13 p0[1] p0[3] p0[7] p0[4] 5 6 7 8 v dd p1[0] p1[7] p1[4] xres p2[5] d? 1 2 3 4 12 11 10 9 table 1. pin definitions ? 16-pin part pinout (qfn) pin no. type name description 1 i/o p2[3] digital i/o, crystal input (xin) 2 i/ohr p1[7] digital i/o, spi ss, i 2 c scl 3 i/ohr p1[5] digital i/o, spi miso, i 2 c sda 4 i/ohr p1[1] [1, 2] digital i/o, issp clk, i 2 c scl, spi mosi 5 power v ss ground connection 6 usb line d+ usb phy 7 usb line d? usb phy 8 power v dd supply 9 i/ohr p1[0] [1, 2] digital i/o, issp data, i 2 c sda, spi clk 10 i/ohr p1[4] digital i/o, optional external clock input (extclk) 11 input xres active high external reset with internal pull-down 12 i/oh p0[4] digital i/o 13 i/oh p0[7] digital i/o 14 i/oh p0[3] digital i/o 15 i/oh p0[1] digital i/o 16 i/o p2[5] digital i/o, crystal output (xout) legend i = input, o = output, oh = 5 ma high output drive, r = regulated output notes 1. during power up or reset event, device p1[0] and p1[1] may disturb the i 2 c bus. use alternate pins if issues are encountered. 2. these are the in-system serial programming (issp) pins that are not high z at power on reset (por).
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 10 of 40 32-pin part pinout figure 7. cy7c64343/cy7c64345 32-pin encore v usb device p0[1] p2[5] p2[3] p2[1] p1[7] qfn ( top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 v ss p0[3] p0[7] v dd p0[6] p0[4] p0[2] p1[5] p1[1] p0[0] p2[6] p3[0] xres d+ d? p1[0] p1[2] p1[4] p1[6] p2[4] p2[2] p2[0] p3[2] p0[5] p1[3] v dd v ss table 2. pin definitions ? 32-pin part pinout (qfn) pin no. type name description 1 i/oh p0[1] digital i/o 2 i/o p2[5] digital i/o, crystal output (xout) 3 i/o p2[3] digital i/o, crystal input (xin) 4 i/o p2[1] digital i/o 5 i/ohr p1[7] digital i/o, i 2 c scl, spi ss 6 i/ohr p1[5] digital i/o, i 2 c sda, spi miso 7 i/ohr p1[3] digital i/o, spi clk 8 i/ohr p1[1] [3, 4] digital i/o, issp clk, i 2 c scl, spi mosi 9 power v ss ground 10 i/o d+ usb phy 11 i/o d? usb phy 12 power v dd supply voltage 13 i/ohr p1[0] [3, 4] digital i/o, issp data, i 2 c sda, spi clk 14 i/ohr p1[2] digital i/o 15 i/ohr p1[4] digital i/o, optional external clock input (extclk) 16 i/ohr p1[6] digital i/o 17 reset xres active high external reset with internal pull down 18 i/o p3[0] digital i/o 19 i/o p3[2] digital i/o 20 i/o p2[0] digital i/o 21 i/o p2[2] digital i/o 22 i/o p2[4] digital i/o 23 i/o p2[6] digital i/o 24 i/oh p0[0] digital i/o 25 i/oh p0[2] digital i/o 26 i/oh p0[4] digital i/o 27 i/oh p0[6] digital i/o 28 power v dd supply voltage 29 i/oh p0[7] digital i/o 30 i/oh p0[5] digital i/o 31 i/oh p0[3] digital i/o 32 power v ss ground cp power v ss ensure the center pad is connected to ground legend i = input, o = output, oh = 5 ma high output drive, r = regulated output notes 3. during power up or reset event, device p1[0] and p1[1] may disturb the i 2 c bus. use alternate pins if issues are encountered. 4. these are the in-system serial programming (issp) pins that are not high z at power on reset (por).
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 11 of 40 48-pin part pinout figure 8. cy7c64355/cy7c64356 48-pin encore v usb device qfn (top view) p0[1] v ss p0[3] p0[5] p0[7] v dd p0[6] 10 11 12 p2[7] p2[5] p2[3] p2[1] p4[3] p4[1] p3[7] p3[5] p3[3] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p0[2] p0[0] p2[6] p2[4] p2[2] p2[0] p3[2] p3[0] xres p1[6] p0[4] 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 nc nc p1[3] p1[1] v ss d+ d- v dd p1[0] p1[2] p1[4] nc p3[1] p1[7] p1[5] p3[4] p3[6] p4[0] p4[2] nc nc table 3. 48-pin part pinout (qfn) pin no. type pin name description 1nc nc no connection 2 i/o p2[7] digital i/o 3 i/o p2[5] digital i/o, crystal out (xout) 4 i/o p2[3] digital i/o, crystal in (xin) 5 i/o p2[1] digital i/o 6 i/o p4[3] digital i/o 7 i/o p4[1] digital i/o 8 i/o p3[7] digital i/o 9 i/o p3[5] digital i/o 10 i/o p3[3] digital i/o 11 i/o p3[1] digital i/o 12 i/ohr p1[7] digital i/o, i 2 c scl, spi ss 13 i/ohr p1[5] digital i/o, i 2 c sda, spi miso 14 nc nc no connection 15 nc nc no connection 16 i/ohr p1[3] digital i/o, spi clk 17 i/ohr p1[1] [5, 6] digital i/o, issp clk, i 2 c scl, spi mosi 18 power v ss supply ground 19 i/o d+ usb 20 i/o d? usb 21 power v dd supply voltage 22 i/ohr p1[0] [5, 6] digital i/o, issp data, i 2 c sda, spi clk 23 i/ohr p1[2] digital i/o notes 5. during power up or reset event, device p1[0] and p1[1] may disturb the i 2 c bus. use alternate pins if issues are encountered. 6. these are the in-system serial programming (issp) pins that are not high z at power on reset (por).
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 12 of 40 24 i/ohr p1[4] digital i/o, optional external clock input (extclk) 25 i/ohr p1[6] digital i/o 26 xres ext reset active high external reset with internal pull down 27 i/o p3[0] digital i/o 28 i/o p3[2] digital i/o 29 i/o p3[4] digital i/o 30 i/o p3[6] digital i/o 31 i/o p4[0] digital i/o 32 i/o p4[2] digital i/o 33 i/o p2[0] digital i/o 34 i/o p2[2] digital i/o 35 i/o p2[4] digital i/o 36 i/o p2[6] digital i/o 37 i/oh p0[0] digital i/o 38 i/oh p0[2] digital i/o 39 i/oh p0[4] digital i/o 40 i/oh p0[6] digital i/o 41 power v dd supply voltage 42 nc nc no connection 43 nc nc no connection 44 i/oh p0[7] digital i/o 45 i/oh p0[5] digital i/o 46 i/oh p0[3] digital i/o 47 power v ss supply ground 48 i/oh p0[1] digital i/o cp power v ss ensure the center pad is connected to ground legend i = input, o = output, oh = 5 ma high output drive, r = regulated output table 3. 48-pin part pinout (qfn) (continued) pin no. type pin name description
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 13 of 40 register reference the section discusses the registers of the encore v device. it lists all the registers in mapping tables, in address order. register conventions the register conventions specific to this section are listed in the following table. register mapping tables the encore v device has a total register address space of 512 bytes. the register space is also referred to as i/o space and is broken into two parts: bank 0 (user space) and bank 1 (configuration space). the xio bi t in the flag register (cpu_f) determines which bank the user is currently in. when the xio bit is set, the user is said to be in the ?extended? address space or the ?configuration? registers. table 4. register conventions convention description r read register or bits w write register or bits l logical register or bits c clearable register or bits # access is bit specific
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 14 of 40 table 5. register map bank 0 table: user space name addr (0, hex) access name addr (0, hex) access name addr (0, hex) access name addr (0, hex) access prt0dr 00 rw ep1_cnt0 40 # 80 c0 prt0ie 01 rw ep1_cnt1 41 rw 81 c1 02 ep2_cnt0 42 # 82 c2 03 ep2_cnt1 43 rw 83 c3 prt1dr 04 rw ep3_cnt0 44 # 84 c4 prt1ie 05 rw ep3_cnt1 45 rw 85 c5 06 ep4_cnt0 46 # 86 c6 07 ep4_cnt1 47 rw 87 c7 prt2dr 08 rw ep5_cnt0 48 # 88 i2c_xcfg c8 rw prt2ie 09 rw ep5_cnt1 49 rw 89 i2c_xstat c9 r 0a ep6_cnt0 4a # 8a i2c_addr ca rw 0b ep6_cnt1 4b rw 8b i2c_bp cb r prt3dr 0c rw ep7_cnt0 4c # 8c i2c_cp cc r prt3ie 0d rw ep7_cnt1 4d rw 8d cpu_bp cd rw 0e ep8_cnt0 4e # 8e cpu_cp ce r 0f ep8_cnt1 4f rw 8f i2c_buf cf rw prt4dr 10 rw 50 90 cur_pp d0 rw prt4ie 11 rw 51 91 stk_pp d1 rw 12 52 92 d2 13 53 93 idx_pp d3 rw 14 54 94 mvr_pp d4 rw 15 55 95 mvw_pp d5 rw 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 pma0_dr 58 rw 98 i2c_dr d8 rw 19 pma1_dr 59 rw 99 d9 1a pma2_dr 5a rw 9a int_clr0 da rw 1b pma3_dr 5b rw 9b int_clr1 db rw 1c pma4_dr 5c rw 9c int_clr2 dc rw 1d pma5_dr 5d rw 9d dd 1e pma6_dr 5e rw 9e int_msk2 de rw 1f pma7_dr 5f rw 9f int_msk1 df rw 20 60 a0 int_msk0 e0 rw 21 61 a1 int_sw_en e1 rw 22 62 a2 int_vc e2 rc 23 63 a3 res_wdt e3 w 24 pma8_dr 64 rw a4 e4 25 pma9_dr 65 rw a5 e5 26 pma10_dr 66 rw a6 e6 27 pma11_dr 67 rw a7 e7 28 pma12_dr 68 rw a8 e8 spi_txr 29 w pma13_dr 69 rw a9 e9 spi_rxr 2a r pma14_dr 6a rw aa ea spi_cr 2b # pma15_dr 6b rw ab eb 2c tmp_dr0 6c rw ac ec 2d tmp_dr1 6d rw ad ed 2e tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 pt0_cfg b0 rw f0 usb_sof0 31 r 71 pt0_data1 b1 rw f1 usb_sof1 32 r 72 pt0_data0 b2 rw f2 usb_cr0 33 rw 73 pt1_cfg b3 rw f3 usbio_cr0 34 # 74 pt1_data1 b4 rw f4 usbio_cr1 35 # 75 pt1_data0 b5 rw f5 ep0_cr 36 # 76 pt2_cfg b6 rw f6 ep0_cnt0 37 # 77 pt2_data1 b7 rw cpu_f f7 rl ep0_dr0 38 rw 78 pt2_data0 b8 rw f8 ep0_dr1 39 rw 79 b9 f9 ep0_dr2 3a rw 7a ba fa ep0_dr3 3b rw 7b bb fb ep0_dr4 3c rw 7c bc fc ep0_dr5 3d rw 7d bd fd ep0_dr6 3e rw 7e be cpu_scr1 fe # ep0_dr7 3f rw 7f bf cpu_scr0 ff # gray fields are reserved; do not access these fields. # access is bit specific.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 15 of 40 table 6. register map bank 1 table: configuration space name addr (1, hex) access name addr (1, hex) access name addr (1, hex) access name addr (1, hex) access prt0dm0 00 rw pma4_ra 40 rw 80 c0 prt0dm1 01 rw pma5_ra 41 rw 81 c1 02 pma6_ra 42 rw 82 c2 03 pma7_ra 43 rw 83 c3 prt1dm0 04 rw pma8_wa 44 rw 84 c4 prt1dm1 05 rw pma9_wa 45 rw 85 c5 06 pma10_wa 46 rw 86 c6 07 pma11_wa 47 rw 87 c7 prt2dm0 08 rw pma12_wa 48 rw 88 c8 prt2dm1 09 rw pma13_wa 49 rw 89 c9 0a pma14_wa 4a rw 8a ca 0b pma15_wa 4b rw 8b cb prt3dm0 0c rw pma8_ra 4c rw 8c cc prt3dm1 0d rw pma9_ra 4d rw 8d cd 0e pma10_ra 4e rw 8e ce 0f pma11_ra 4f rw 8f cf prt4dm0 10 rw pma12_ra 50 rw 90 d0 prt4dm1 11 rw pma13_ra 51 rw 91 d1 12 pma14_ra 52 rw 92 eco_enbus d2 rw 13 pma15_ra 53 rw 93 eco_trim d3 rw 14 ep1_cr0 54 # 94 d4 15 ep2_cr0 55 # 95 d5 16 ep3_cr0 56 # 96 d6 17 ep4_cr0 57 # 97 d7 18 ep5_cr0 58 # 98 mux_cr0 d8 rw 19 ep6_cro 59 # 99 mux_cr1 d9 rw 1a ep7_cr0 5a # 9a mux_cr2 da rw 1b ep8_cr0 5b # 9b mux_cr3 db rw 1c 5c 9c io_cfg1 dc rw 1d 5d 9d out_p1 dd rw 1e 5e 9e io_cfg2 de rw 1f 5f 9f mux_cr4 df rw 20 60 a0 osc_cr0 e0 rw 21 61 a1 eco_cfg e1 # 22 62 a2 osc_cr2 e2 rw 23 63 a3 vlt_cr e3 rw 24 64 a4 vlt_cmp e4 r 25 65 a5 e5 26 66 a6 e6 27 67 a7 e7 28 68 a8 imo_tr e8 w spi_cfg 29 rw 69 a9 ilo_tr e9 w 2a 6a aa ea 2b 6b ab slp_cfg eb rw 2c tmp_dr0 6c rw ac slp_cfg2 ec rw 2d tmp_dr1 6d rw ad slp_cfg3 ed rw 2e tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef usb_cr1 30 # 70 b0 f0 31 71 b1 f1 32 72 b2 f2 33 73 b3 f3 pma0_wa 34 rw 74 b4 f4 pma1_wa 35 rw 75 b5 f5 pma2_wa 36 rw 76 b6 f6 pma3_wa 37 rw 77 b7 cpu_f f7 rl pma4_wa 38 rw 78 b8 f8 pma5_wa 39 rw 79 b9 f9 pma6_wa 3a rw 7a ba imo_tr1 fa rw pma7_wa 3b rw 7b bb fb pma0_ra 3c rw 7c bc fc pma1_ra 3d rw 7d usb_misc_cr bd rw fd pma2_ra 3e rw 7e be fe pma3_ra 3f rw 7f bf ff gray fields are reserved; do not access these fields. # access is bit specific.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 16 of 40 electrical specifications this section presents the dc and ac electrical specifications of the encore v usb devices. for the most up-to-date electrical specifications, verify that you have t he most recent data sheet available by visiting the company web site at http://www.cypress.com figure 9. voltage versus cpu frequency figure 10. imo frequency trim options 5.5v 5.7 mhz 24 mhz cpu frequency vdd voltage 3.0v v a l i d o p e r a t i n g re g i o n 5.5v 750 khz 6 mhz 24 mhz imo frequency vdd voltage 3 mhz 3.0v slimo mode = 01 12 mhz slimo mode = 00 slimo mode = 10
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 17 of 40 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature table 7. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature [10] higher storage temperatures reduces data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 85 ? c degrades reliability. ?55 +25 +125 c v dd supply voltage relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tristate v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma esd electrostatic discharge voltage human body model esd 2000 ? ? v lu [8] latch up current in accordance with jesd78 standard ? ? 200 ma table 8. operating temperature symbol description conditions min typ max units t ai ambient industrial temperature ?40 ? +85 c t ac ambient commercial temperature 0 ? +70 c t ji operational industrial die temperature [11] the temperature rise from ambient to junction is package specific. refer the table thermal impedances per package on page 31 . the user must limit the power consumption to comply with this requirement. ?40 ? +100 c t jc operational commercial die temperature the temperature rise from ambient to junction is package specific. refer the table thermal impedances per package on page 31 . the user must limit the power consumption to comply with this requirement. 0 ? +85 c notes 7. when v dd remains in the range from 1.71 v to 1.9 v for more than 50 sec, the slew rate when moving from the 1.71 v to 1.9 v range to g reater than 2 v must be slower than 1 v/500 sec to avoid triggering por. the only other restriction on slew rates for any other voltage range or trans ition is the srpower_up parameter. 8. errata: for port 1 pins p1[1], p1[4], and p1[5] 300 ohm exte rnal resistor is needed to meet this spec. refer to ?errata? on page 35 for more details. 9. if powering down in standby sleep mode, to properly detect and recover from a v dd brown out condition any of the following actions must be taken: ? bring the device out of sleep before powering down. ? assure that v dd falls below 100 mv before powering back up. ? set the no buzz bit in the osc_cr0 register to keep the voltage monitoring circuit powered during sleep. ? increase the buzz rate to assu re that the falling edge of v dd is captured. the rate is configured through the pssdc bits in the slp_cfg register. for the referenced registers, refer to the encore v technical reference manual. in deep sleep mode, additional low power voltag e monitoring circuitry allows v dd brown out conditions to be detected for edge rates slower than 1 v/ms.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 18 of 40 dc electrical characteristics dc chip level specifications ta b l e 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 9. dc chip level specifications symbol description conditions min typ max units v dd operating voltage [7, 9] no usb activity. 3.0 ? 5.5 v i dd24,3 supply current, cpu = 24 mhz conditions are v dd = 3.0 v, t a = 25 ? c, cpu = 24 mhz, no usb/i 2 c/spi. ? 2.9 4.0 ma i dd12,3 supply current, cpu = 12 mhz conditions are v dd = 3.0 v, t a = 25 ? c, cpu = 12 mhz, no usb/i 2 c/spi. ? 1.7 2.6 ma i dd6,3 supply current, cpu = 6 mhz conditions are v dd = 3.0 v, t a = 25 ? c, cpu = 6 mhz, no usb/i 2 c/spi. ? 1.2 1.8 ma i sb1,3 standby current with por, lvd, and sleep timer v dd = 3.0 v, t a = 25 ? c, i/o regulator turned off. ? 1.1 1.5 ? a i sb0,3 deep sleep current v dd = 3.0 v, t a = 25 ? c, i/o regulator turned off. ? 0.1 ? ? a v ddusb operating voltage usb activity, usb regulator enabled 4.35 ? 5.25 v i dd24,5 supply current, cpu = 24 mhz conditions are v dd = 5.0 v, t a = 25 ? c, cpu = 24 mhz, imo = 24 mhz usb active, no i 2 c/spi. ? 7.1 ? ma i dd12,5 supply current, cpu = 12 mhz conditions are v dd = 5.0 v, t a = 25 ? c, cpu = 12 mhz, imo = 24 mhz usb active, no i 2 c/spi. ? 6.2 ? ma i dd6,5 supply current, cpu = 6 mhz conditions are v dd = 5.0 v, t a = 25 ? c, cpu = 6 mhz, imo = 24 mhz usb active, no i 2 c/spi ? 5.8 ? ma i sb1,5 standby current with por, lvd, and sleep timer v dd = 5.0 v, t a = 25 ? c, i/o regulator turned off. ? 1.1 ? ? a i sb0,5 deep sleep current v dd = 5.0 v, t a = 25 ? c, i/o regulator turned off. ? 0.1 ? ? a v ddusb operating voltage usb activity, usb regulator bypassed 3.15 3.3 3.60 v notes 10. higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 85 c degrade reliability. 11. the temperature rise from ambient to junction is package specific. see package handling on page 31 . the user must limit the power consumption to comply with this requirement.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 19 of 40 adc electrical specifications table 10. dc characteristics ? usb interface symbol description conditions min typ max units rusbi usb d+ pull-up resistance with idle bus 0.900 ? 1.575 k ? rusba usb d+ pull-up resistance while receiving traffic 1.425 ? 3.090 k ? vohusb static output high 2.8 ? 3.6 v volusb static output low ? ? 0.3 v vdi differential input sensitivity 0.2 ? ? v vcm differential input common mode range 0.8 ? 2.5 v vse single-ended receiver threshold 0.8 ? 2.0 v cin transceiver capacitance ? 50 pf iio high z state data line leakage on d+ or d? line ?10 ? +10 ? a rps2 ps/2 pull up resistance 3 5 7 k ? rext external usb series resistor in series with each usb pin 21.78 22.0 22.22 ? table 11. adc user module electrical specifications symbol description conditions min typ max units input v in input voltage range 0 ? vrefadc v c iin input capacitance ? ? 5 pf r in input resistance equiva lent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500ff* data clock) 1/(400ff* data clock) 1/(300ff* data clock) ? reference v refadc adc reference voltage 1.14 ? 1.26 v conversion rate f clk data clock source is chip?s internal main oscillator. see ac chip-level specifications for accuracy 2.25 ? 6 mhz s8 8-bit sample rate da ta clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 23.4375 ? ksps s10 10-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 5.859 ? ksps dc accuracy res resolution can be set to 8-, 9-, or 10-bit 8 ? 10 bits dnl differential nonlinearity ?1 ? +2 lsb inl integral nonlinearity ?2 ? +2 lsb e offset offset error 8-bit resolution 0 3.2 19.2 lsb 10-bit resolution 0 12.8 76.8 lsb e gain gain error for any resolution ?5 ? +5 %fsr power i adc operating current ? 2.1 2.6 ma psrr power supply rejection ratio psrr ( v dd > 3.0 v) ? 24 ? db psrr ( v dd < 3.0 v) ? 30 ? db
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 20 of 40 dc general purpose i/o specifications ta b l e 1 2 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 3.0 v to 5.5 v and package specific temperature range. typical parameters apply to 5 v and 3.3 v at 25 c. these are for design guidance only. table 12. 3.0 v and 5.5 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor 4 5.6 8 k ? v oh1 high output voltage port 2 or 3 pins i oh < 10 a, maximum of 10 ma source current in all i/os. v dd ? 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins i oh = 1 ma, maximum of 20 ma source current in all i/os. v dd ? 0.9 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled i oh < 10 a, maximum of 10 ma source current in all i/os. v dd ? 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled i oh = 5 ma, maximum of 20 ma source current in all i/os. v dd ? 0.9 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh < 10 ? a, v dd > 3.1 v, maximum of 4 i/os all sourcing 5 ma 2.85 3.00 3.3 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh = 5 ma, v dd > 3.1 v, maximum of 20 ma source current in all i/os 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh < 10 ? a, v dd > 3.0 v, maximum of 20 ma source current in all i/os 2.35 2.50 2.75 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh = 2 ma, v dd > 3.0 v, maximum of 20 ma source current in all i/os 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, v dd > 3.0 v, maximum of 20 ma source current in all i/os 1.60 1.80 2.1 v v oh10 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, v dd > 3.0 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage i ol = 25 ma, v dd > 3.3 v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]). ? ? 0.75 v v il input low voltage ? ? 0.8 v v ih input high voltage 2.0 ? ? v v h input hysteresis voltage ?80? mv i il input leakage (absolute value) ? 0.001 1 a c pin pin capacitance package and pin dependent. te m p = 2 5 ? c . 0.5 1.7 5 pf
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 21 of 40 dc por and lvd specifications ta b l e 1 3 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. dc programming specifications ta b l e 1 4 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 13. dc por and lvd specifications symbol description conditions min typ max units v ppor v dd value for ppor trip [12] porlev[1:0] = 10b ? 2.82 2.95 v v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b ? ? 2.85 2.95 3.06 ?- ? 4.62 ? ? 2.92 3.02 3.13 ? ? 4.73 ? ? 2.99 3.09 3.20 ? ? 4.83 v v v v v v v v table 14. dc programming specifications symbol description conditions min typ max units v ddiwrite supply voltage for flash write operations 1.71 ? 5.25 v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify see appropriate dc general purpose i/o specifications table ? ? v il v v ihp input high voltage during programming or verify 1.71 ? v ddiwrite + 0.3 v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify [13] ? ? 0.2 ma i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify [13] ? ? 1.5 ma v olp output low voltage during programming or verify ? ? v ss + 0.75 v v ohp output high voltage during programming or verify v ddiwrite ? 0.9 ? v ddiwrite v flash enpb flash write endurance [14] 50,000 ? ? cycles flash dr flash data retention [15] 10 20 ? years notes 12. always greater than 50 mv above v ppor (porlev = 10) for falling supply. 13. driving internal pull down resistor. 14. erase/write cycles per block. 15. following maximum flash write cycles at tamb = 55 c and tj = 70 c.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 22 of 40 ac electrical characteristics ac chip level specifications the following tables list guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 15. ac chip level specifications symbol description conditions min typ max units f cpu processing frequency [16] 5.7 ? 25.2 mhz f 32k1 internal low-speed oscillator (ilo) frequency trimmed [17] 19 32 50 khz f 32k_u ilo untrimmed frequency) 13 32 82 khz f 32k2 ilo frequency untrimmed 13 32 82 khz f imo24 internal main oscillator (imo) stability for 24 mhz 5% (12) 22.8 24 25.2 mhz f imo12 imo stability for 12 mhz [17] 11.4 12 12.6 mhz f imo6 imo stability for 6 mhz [17] 5.7 6.0 6.3 mhz dc imo duty cycle of imo 40 50 60 % dc ilo ilo duty cycle 40 50 60 % sr power_up power supply slew rate ? ? 250 v/ms t xrst external reset pulse width at power-up after supply voltage is valid 1 ? ? ms t xrst2 external reset pulse width after power-up [18] applies after part has booted 10 ? ? ? s table 16. ac characteristics ? usb data timings symbol description conditions min typ max units tdrate full speed data rate average bit rate 11.97 12 12.03 mhz tdjr1 receiver data jitter tolerance to next transition ?18.5 ? 18.5 ns tdjr2 receiver data jitter tolerance to pair transition ?9 ? 9 ns tudj1 driver differential jitter to next transition ?3.5 ? 3.5 ns tudj2 driver differential jitter to pair transition ?4.0 ? 4.0 ns tfdeop source jitter for differential transition to se0 transition ?2 ? 5 ns tfeopt source se0 interval of eop 160 ? 175 ns tfeopr receiver se0 interval of eop 82 ? ? ns tfst width of se0 interval during differential transition ??14ns table 17. ac characteristics ? usb driver symbol description conditions min typ max units tr transition rise time 50 pf 4 ? 20 ns tf transition fall time 50 pf 4 ? 20 ns tr [19] rise/fall time matching 90.00 ? 111.1 % vcrs output signal crossover voltage 1.3 ? 2.0 v notes 16. v dd = 3.0 v and t j = 85 ? c, cpu speed. 17. trimmed for 3.3 v operation using factory trim values. 18. the minimum required xres pulse length is longer when programming the device (see table 20 on page 24 ). 19. errata: rising to falling rate matching of the usb d+ and d- lines has a corner case issue when operating voltage is below 3.3 v. refer to ?errata? on page 35 for more details.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 23 of 40 ac general purpose i/o specifications ta b l e 1 8 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. figure 11. gpio timing diagram ac external clock specifications ta b l e 1 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 18. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode, ports 0, 1 ? ? 12 mhz trise23 rise time, strong mode ports 2, 3 v dd = 3.0 to 3.6 v, 10% - 90% 15 ? 80 ns trise01 rise time, strong mode ports 0, 1 v dd = 3.0 to 3.6 v, 10% - 90% 10 ? 50 ns tfall fall time, strong mode all ports v dd = 3.0 to 3.6 v, 10% - 90% 10 ? 50 ns tfall trise23 trise01 90% 10% gpio pin output voltage table 19. ac external clock specifications symbol description conditions min typ max units f oscext frequency 0.750 ? 25.2 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power-up imo to switch 150 ? ? ? s
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 24 of 40 ac programming specifications ta b l e 2 0 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. figure 12. timing diagra m - ac programming cycle table 20. ac programming specifications symbol description conditions min typ max units t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? ? 18 ms t write flash block write time ? ? 25 ms t dsclk1 data out delay from falling edge of sclk, v dd > 3.6 v ? ? 60 ns t dsclk2 data out delay from falling edge of sclk 3.0 v < v dd < 3.6 v ? ? 85 ns t xrst3 external reset pulse width after power-up required to enter programming mode when coming out of sleep 263 ? ? ? s
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 25 of 40 ac i 2 c specifications ta b l e 2 1 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. figure 13. definition of timing for fast/standard mode on the i 2 c bus table 21. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 ?0.6 ? ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? ? s t highi2c high period of the scl clock 4.0 ?0.6 ? ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? ? s t hddati2c data hold time 0 ?0 ? ? s t sudati2c data setup time 250 ? 100 [20] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? ? s t spi2c pulse width of spikes are s uppressed by the input filter ? ? 0 50 ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c note 20. a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement t sudat ? 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t sudat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 26 of 40 figure 14. spi master mode 0 and 2 figure 15. spi master mode 1 and 3 table 22. spi master ac specifications symbol description conditions min typ max units f sclk sclk clock frequency ? ? 6 mhz dc sclk duty cycle ? 50 ? % t setup miso to sclk setup time 60 ? ? ns t hold sclk to miso hold time 40 ? ? ns t out_val sclk to mosi valid time ? ? 40 ns t out_h sclk to mosi hold time 40 ? ? ns 1/f sclk t low t high t out_h t hold t setup t out_su msb lsb spi master, modes 0 and 2 sclk (mode 0) sclk (mode 2) miso (input) mosi (output) 1/f sclk t high t low t out_h t hold t setup sclk (mode 1) sclk (mode 3) miso (input) mosi (output) spi master, modes 1 and 3 t out_su msb msb lsb lsb
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 27 of 40 figure 16. spi slave mode 0 and 2 table 23. spi slave ac specifications symbol description conditions min typ max units f sclk sclk clock frequency 0.0469 ? 12 mhz t low sclk low time 41.67 ? ? ns t high sclk high time 41.67 ? ? ns t setup mosi to sclk setup time 30 ? ? ns t hold sclk to mosi hold time 50 ? ? ns t ss_miso ss low to miso valid ? ? 153 ns t sclk_miso sclk to miso valid ? ? 125 ns t ss_high ss high time 50 ? ? ns t ss_clk time from ss low to first sclk 2/f sclk ??ns t clk_ss time from last sclk to ss high 2/f sclk ??ns t clk_ss t ss_high 1/f sclk t low t high t out_h t hold t setup t ss_miso t ss_clk msb lsb spi slave, modes 0 and 2 /ss sclk (mode 0) sclk (mode 2) miso (output) mosi (input)
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 28 of 40 figure 17. spi slave mode 1 and 3 t clk_ss 1/f sclk t high t low t sclk_miso t out_h t hold t setup t ss_clk /ss sclk (mode 1) sclk (mode 3) miso (output) mosi (input) spi slave, modes 1 and 3 t ss_miso msb msb lsb lsb
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 29 of 40 package diagram this section illustrates the packaging spec ifications for the encore v usb device, along with the thermal impedances for each package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the encore v emulation tools and their dimensions, refer to the development kit. packaging dimensions figure 18. 16-pin chip on lead (3 3 0.6 mm) lg16a/ld16a (sawn) package outline, 001-09116 001-09116 *i
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 30 of 40 figure 19. 32-pin qfn (5 5 0.55 mm) lq32 3.5 3.5 e-pad (sawn) package outline, 001-42168 figure 20. 48-pin qfn (7 7 1.00 mm) lt48a 5.1 5.1 e-pad (sawn) package outline, 001-13191 001-42168 *e 001-13191 *g
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 31 of 40 package handling some ic packages require baking before they are soldered onto a pcb to remove moisture that may have been absorbed after leavin g the factory. a label on the package has details about the actual bake temperature and the minimum bake time to remove this mois ture. the maximum bake time is the aggregate time that the parts exposed to the bake temper ature. exceeding this exposure may degrade device reliability. thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 24. package handling parameter description minimum typical maximum unit t baketemp bake temperature ? 125 see package label ? c t baketime bake time see package label ? 72 hours table 25. thermal impedances per package package typical ? ja [21] 16-pin qfn 32.69 ? c / w 32-pin qfn [22] 19.51 ? c / w 48-pin qfn [22] 17.68 ? c / w table 26. typical package capacitance on crystal pins package package capacitance 32-pin qfn 3.2 pf 48-pin qfn 3.3 pf table 27. solder reflow peak temperature package minimum peak temperature [23] maximum peak temperature 16-pin qfn 240 ? c 260 ? c 32-pin qfn 240 ? c 260 ? c 48-pin qfn 240 ? c 260 ? c notes 21. t j = t a + power x ? ja. 22. to achieve the thermal impedance specif ied for the package, solder the center thermal pad to the pcb ground plane. 23. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 c with s n-pb or 245 5 c with sn-ag-cu paste. refer to the solder manufacturer specifications.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 32 of 40 ordering information table 28. ordering code - commercial parts ordering code package information flash (kb) sram (kb) no. of gpios target applications cy7c64315-16lkxc 16-pin qfn (3 3 mm) 16 1 11 mid-tier full-speed usb dongle, remote control host module, various cy7c64315-16lkxct 16-pin qfn (tape and reel), (3 3 mm) 16 1 11 mid-tier full-speed usb dongle, remote control host module, various cy7c64316-16lkxc 16-pin qfn (3 3 mm) 32 2 11 feature-rich full-speed usb dongle, remote control host module, various cy7c64316-16lkxct 16-pin qfn (tape and reel), (3 3 mm) 32 2 11 feature-rich full-speed usb dongle, remote control host module, various cy7c64343-32lqxc 32-pin qfn (5 5 mm) 8 1 25 full-speed usb mouse, various cy7c64343-32lqxct 32-pin qfn (tape and reel), (5 5 mm) 8 1 25 full-speed usb mouse, various cy7c64345-32lqxc 32-pin qfn (5 5 mm) 16 1 25 full-speed usb mouse, various cy7c64345-32lqxct 32-pin qfn (tape and reel), (5 5 mm) 16 1 25 full-speed usb mouse, various CY7C64355-48LTXC 48-pin qfn (7 7 mm) 16 1 36 full-speed usb keyboard, various CY7C64355-48LTXCt 48-pin qfn (tape and reel), (7 7 mm) 16 1 36 full-speed usb keyboard, various cy7c64356-48ltxc 48-pin qfn (7 7 mm) 32 2 36 feature-rich full-speed usb keyboard, various cy7c64356-48ltxct 48-pin qfn (tape and reel), (7 7 mm) 32 2 36 feature-rich full-speed usb keyboard, various table 29.ordering code - industrial parts ordering code package information flash (kb) sram (kb) no. of gpios target applications cy7c64315-16lkxi 16-pin qfn, industrial (3 3 mm) 16 1 11 mid-tier full-speed usb dongle, remote control host module, various cy7c64315-16lkxit 16-pin qfn, industrial (tape and reel), (3 3 mm) 16 1 11 mid-tier full-speed usb dongle, remote control host module, various cy7c64343-32lqxi 32-pin qfn, industrial (5 5 0.55 mm) 8 1 25 full-speed usb mouse, various cy7c64343-32lqxit 32-pin qfn, industrial (tape and reel), (5 5 mm) 8 1 25 full-speed usb mouse, various cy7c64345-32lqxi 32-pin qfn, industrial (5 5 mm) 16 1 25 full-speed usb mouse, various cy7c64345-32lqxit 32-pin qfn, industrial (tape and reel), (5 5 mm) 16 1 25 full-speed usb mouse, various cy7c64356-48ltxi 48-pin qfn, industrial (7 7 mm) 32 2 36 feature-rich full-speed usb keyboard, various cy7c64356-48ltxit 48-pin qfn, industrial (tape and reel), (7 7 mm) 32 2 36 feature-rich full-speed usb keyboard, various
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 33 of 40 ordering code definitions cy marketing code: 7c64 = encore full-speed usb controller 7c64 company id: cy = cypress xxx - xx xxx package type: lk/lq/lt: qfn pb-free c/i temperature range: commercial/industrial base part number pin count: 16 = 16 pins, 32 = 32 pins, 48 = 48 pins (t) tape and reel
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 34 of 40 acronyms document conventions units of measure numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or ?0x? are decimal. acronym description api application programming interface cpu central processing unit gpio general purpose i/o ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator i/o input/output lsb least significant bit lvd low voltage detect msb most significant bit por power on reset ppor precision power on reset psoc programmable system-on-chip slimo slow imo sram static random access memory symbol unit of measure ? c degree celsius db decibel ff femtofarad hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz k ? kilohm mhz megahertz m ? megaohm ? a microampere ? f microfarad ? h microhenry ? s microsecond ? v microvolt ? vrms microvolts root-mean-square ? w microwatt ma milliampere ms milli-second mv millivolt na nanoampere ns nanosecond nv nanovolt w ohm pa picoampere pf picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second s sigma: one standard deviation v volt
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 35 of 40 errata this section describes the errata for the encore v ? cy7c643xx. details include errata trigger conditions, scope of impact, ava ilable workaround, and silicon revision applicability. contact your local cypress sales re presentative if you have questions. cy7c643xx errata summary the following errata item applies to the cy7c643xx data sheets. 1. latch up susceptibility when ma ximum i/o sink current exceeded problem definition p1[3], p1[6], and p1[7] pins are susceptible to latch up when the i/o sink curren t exceeds 25 ma per pin on these pins. parameters affected lu ? latch up current. per jesd78a, the maximum allowable latch up current per pin is 100 ma. cypress internal specification is 200 ma latch up current limit. trigger conditions latch up occurs when both the following conditions are met: a. the offending i/o is externally connected to a voltage higher than the i/o high state, causing a current to flow into the pin that exceeds 25 ma. b. a port1 i/o (p1[1], p1[4], and p1[5] res pectively) adjacent to the offending i/o is connected to a voltage lower than the i/o low state. this causes a signal that dr ops below vss (signal undershoot) and a current greater than 200 ma to flow out of the pin. scope of impact the trigger conditions outlined in this item exceed the maximum ratings specified in the cy7c643xx data sheets. workaround add a series resistor > 300 ? to p1[3], p1[6], and p1[7] pins to restrict current to within latch up limits. fix status this issue will be corrected in the next new silicon revision. 2. does not meet usb 2.0 specification for d+ and d- ri se/fall matching when supply voltage is under 3.3 v problem definition rising to falling rate matching of the usb d+ and d- lines has a corner case at lower supply voltages, such as those under 3.3 v. parameters affected rising to falling rate matching of the usb data lines. trigger condition(s) operating the vcc supply voltage at the lo w end of the chip?s specification (under 3.3 v) may cause a mismatch in the rising to falling rate. scope of impact this condition does not affect usb commun ications but could cause corner case issues with usb lines? rise/fall matching specification. signal integrity tests we re run using the cypress development kit and excellent eye was observed with supply voltage of 3.15 v.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 36 of 40 figure 21. eye diagram workaround avoid the trigger condition by using lower tolerance voltage regulators. fix status this issue will not be corrected in the next new silicon revision.
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 37 of 40 document history page document title: cy7c6431x, cy7c6434x, cy7c 6435x, encore? v full speed usb controller document number: 001-12394 rev. ecn no. orig. of change submission date description of change ** 626256 tyj see ecn new data sheet. *a 735718 tyj / ari see ecn filled in tbds, added new block diagram, and corrected some values. part numbers updated as per new specifications. *b 1120404 ari see ecn corrected the block diagram and figure 3, which is the 16-pin encore v device. corrected the description to pin 29 on table 2, the typ/max values for i sb0 on the dc chip-level specifications , the current value for the latch-up current in the electrical characterist ics section, and corrected the 16 qfn package information in the thermal impedance table. corrected some of the bulleted items on the first page. added dc characteristics?usb interface table. added ac characteristics?usb data timings table. added ac characteristics?usb driver table. corrected flash write endurance minimum value in the dc programming specifications table. corrected the flash erase time max va lue and the flash block write time max value in the ac programming specifications table. implemented new latest template. include parameters: vcrs, rpu (usb, active), rpu (usb suspend), tfdeop, tfeopr2, tfeopt, tfst. added register map tables. corrected a value in the dc chip-level specifications table. *c 1241024 tyj / ari see ecn corrected idd values in table 6 - dc chip-level specifications. *d 1639963 aesa see ecn post to www.cypress.com *e 2138889 tyj / pyrs see ecn updated ordering code table: - ordering code changed for 32-qfn package: from -32lkxc to -32ltxc - added a new package type ? ?ltxc? for 48-qfn - included tape and reel ordering code for 32-qfn and 48-qfn packages changed active current values at 24, 12 and 6mhz in table ?dc chip-level specifications? - idd24: 2.15 to 3.1ma - idd12: 1.45 to 2.0ma - idd6: 1.1 to 1.5ma added information on using p1[0] and p1[1] as the i2c interface during por or reset events
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 38 of 40 *f 2583853 tyj / pyrs / hmt 10/10/08 converted from preliminary to final added operating voltage ranges with usb adc resolution changed from 10-bit to 8-bit rephrased battery monitoring clause in page 1 to include ?with external components? included adc specifications table included voh7, voh8, voh9, voh10 specs flash data retention ? condition added to note [11] input leakage spec changed to 25 na max under ac char, frequency accuracy of ilo corrected gpio rise time for ports 0,1 and ports 2,3 made common ac programming specifications updated included ac programmi ng cycle timing diagram ac spi specification updated spec change for 32-qfn package input leakage current maximum value changed to 1 ? a updated v ohv parameter in table 13 updated thermal impedances for the packages update development tools, add designing with psoc designer. edit, fix links and table format. update tms. *g 2653717 dvja / pyrs 02/04/09 updated features, functional overview, development tools, and designing with psoc designer sections with edits. removed ?gui - graphical user inte rface? from document conventions acronym table. removed ?o - only a read/write register or bits? in table 4 edited table 8: removed 10-bit resolution information and corrected units column. added package handling section added 8k part ?cy7c64343-32lqxc? to ordering information. *h 2714694 dvja / aesa 06/04/2009 updated block diagram. added full speed usb, 10-bit adc, spi, and i2c slave sections. adc resolution changed from 8-bit to 10-bit updated table 9 dc chip level specs updated table10 dc char - usb interface updated table 12 dc por and ldv specs changed operating temperature from commercial to industrial changed temperature range to industrial: ?40 to 85c figure 9: changed minimum cpu fre quency from 750 khz to 5.7 mhz table 14: removed ?maximum? from the f cpu description ordering information: replaced ?c? with ?i ? in all part numbers to denote indus- trial temp range *i 2764460 dvja / aesa 09/16/2009 changed table 12: adc specs added f 32k2 (untrimmed) spec to table 16: ac chip level specs changed t ramp spec to sr power_up in table 16: ac chip level specs added table 27: typical package capacitance on crystal pins *j 2811903 dvja 11/20/2009 added usb-if tid number in features on page 1 . added note 5 on page 18. changed v ihp in table 15 on page 22 . document history page (continued) document title: cy7c6431x, cy7c6434x, cy7c 6435x, encore? v full speed usb controller document number: 001-12394 rev. ecn no. orig. of change submission date description of change
cy7c6431x cy7c6434x cy7c6435x document number: 001-12394 rev. *r page 39 of 40 *k 2874274 kku / pyrs 02/05/10 on page 4, changed the input voltage range from ?0 v to 1.3 v? to ?0 v to v refadc ?. added note for operating voltage in table 9 . updated register map. added spi slave and master mode diagrams; in ta b l e 2 2 , changed t out_high parameter to t out_h and modified description; in ta b l e 2 3 , updated t ss_clk and t clk_ss min values to 2/f sclk and changed description of t ss_miso . added vdd usb parameter in ta b l e 9 . updated package diagrams. *l 3028310 xut 09/13/2010 removed hpor bit reference from dc por and lvd specifications updated development tools and designing with psoc designer . added ordering code definitions moved acronyms and document conventions to end of document. *m 3048308 nxz 10/06/2010 updated features section as furnished in the cdt 74890 updated datasheet as per new template all footnotes upd ated sequentially *n 3557631 csai 03/21/2012 updated getting started . updated package diagram . updated in new template. *o 3912957 nxz 03/06/2013 updated functional overview (updated the encore v core (updated contents in the section), updated full-speed usb (updated contents in the section)). updated register mapping tables (updated ta b l e 6 (replaced ?ec0_enbus? with ?eco_enbus? and replaced ?ec0_trim? with ?eco_trim?)). updated package diagram : spec 001-09116 ? changed revision from *f to *h. spec 001-42168 ? changed revision from *d to *e. spec 001-13191 ? changed revision from *f to *g. *p 3979449 ankc 04/23/2013 added errata . *q 4074443 ankc 07/23/2013 added erra ta footnotes (note 8, 19). updated electrical specifications : updated absolute maximum ratings : added note 8 and referred the same note in lu parameter. updated ac electrical characteristics updated ac chip level specifications : added note 19 and referred the same note in tr parameter in ta b l e 1 7 . updated in new template. *r 4197134 ankc 11/20/2013 updated package diagram : spec 001-09116 ? changed revision from *h to *i. completing sunset review. document history page (continued) document title: cy7c6431x, cy7c6434x, cy7c 6435x, encore? v full speed usb controller document number: 001-12394 rev. ecn no. orig. of change submission date description of change
document number: 001-12394 rev. *r revised november 20, 2013 page 40 of 40 psoc designer? is a trademark and psoc? and capsense? are registered trademarks of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c6431x cy7c6434x cy7c6435x ? cypress semiconductor corporation, 2006-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reaso nably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufact urer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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